// PC GAMER — GAMING
AMD's Zen 6 gaming CPUs might be absolute monsters by the looks of the server chips—and there's a 3D V-Cache variant to keep an eye on
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AMD has revealed a substantial amount of detail on its next-gen Zen 6 CPU architecture, in the form of a technical deep dive on its newly-unveiled EPYC "Venice" range of server chips.
These models will find themselves buried deep within data centers, but the Zen 6 architecture itself looks extremely promising for next-gen Ryzen desktop processors—and quite possibly, your next gaming CPU.
Current Zen 5 CCDs with full-fat performance cores max out at eight cores per chiplet, but a single Zen 6 CCD, based on TSMC’s cutting-edge N2P node, is stuffed with 12 of the beasties—alongside 4 MB of L3 cache per core, the same as Zen 5. That adds up to a total of 48 MB of L3 cache per CCD, as opposed to the 32 MB you'd find on an 8-core Zen 5 chip (via Techpowerup).
A current gen Zen 5 CPU with more than eight cores has to spread them across two CCDs, which can result in latency as the two communicate with each other during multi-threaded tasks. With the upped core count per CCD, a 12-core Zen 6 chip would face no such performance penalty.
It's the "c" core counts that have received the biggest jump in density, though. These aren't the same as Intel's Efficiency cores, instead amounting to scaled down performance cores designed to take up less die space and spread the workload during heavily multi-threaded tasks.
In the case of Zen 6c, 32 cores can be squeezed onto a single core complex, double that of a Zen 5 equivalent. The L3 cache per Zen 6c core has been upped, too, from 2 MB per core to 4 MB. That means a fully-stocked 32-core Zen 6c complex ends up with a stonking 128 MB of L3 cache to play with, quadruple that of a maxed-out Zen 5c version.
In terms of clock speeds, the full-fat Zen 6 cores on a Venice server chip have a maximum clock frequency of 5.3 GHz, while the Zen 6c cores top out at 4.1 GHz. Rumours suggest the eventual Zen 6-based Ryzen desktop chips will top out much higher than that, potentially above 6 GHz, although we'll have to wait and see in that regard.
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AMD has also improved Zen 6's branch prediction, with optimized prediction tables and larger prediction queues, while the return address stack has also been buffed from 52 to 64 entries, alongside two branch predictions per cycle. In essence, Zen 6 should be better at anticipating instructions, and should also recover faster from errors. The reorder buffer, integer physical register, and operation cache sizes have been increased, too.